1. Field of the Invention
This invention relates generally to an electronic device, and, more specifically, to providing a voltage translator for transitioning from a first voltage level to a second voltage level.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly, densely packed electrically conducting lines may also be formed in the semiconductor substrate. By forming selected electrical connections between selected semiconductor devices and selected conducting lines, circuits capable of performing complex functions may be created. For example, bits of data may be stored by providing electrical current to a plurality of bit lines and an orthogonal plurality of wordlines that may be electrically coupled to one or more capacitors in a semiconductor memory.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets, of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity, may be divided into 64 sub-arrays, each having 256K (218) memory cells.
In electronic devices today, many integrated circuit chips use designs that are used to promote savings and power consumption. This is particularly true for mobile and wireless type devices. Many times, devices, such as microprocessors, memories, and other integrated circuit chips are designed to operate at lower operating voltages. Often, more than one operating voltage may be implemented into a single integrated circuit chip. There are various portions of a circuit that are implemented into an integrated circuit chip that, for various reasons, operate at different voltage levels. These reasons may include operating speed, type of devices being used in the circuit, efficient switching voltages, and the like.
In order to provide efficient operation of a device, such as an integrated circuit chip, a transition between various operating voltage modes is desirable. For example, operation from the operating range of VCC to ground may be modified for operation from VCC to VBB, wherein VBB may be a voltage level that is above or below ground. Therefore, efficient switching to and from VCC-ground operating levels to VCC–VBB is desirable. State-of-the-art designs implement a switching between various voltage levels, however, many inefficiencies may result, including current leakage and slow transitions in the designs of today.
In order to translate operating voltages, designers have implemented inverters that translate an operating voltage from VCC to ground to a second inverter that translates from VCC to VBB. However, this proves to be problematic since it is difficult to completely shut off the second inverter stage since the voltage generally does not fall all the way to ground. In other words, with two inverters, one inverter has a negative node tied to ground, and when the input of that inverter goes to logic high, the output will go to ground. However, when the second input to the second inverter goes to VBB there is a leakage current since a positive voltage on the second inverter exists. To overcome this problem, designers have moved towards a translator type design that translates voltage levels.
Turning now to FIG. 1, a typical prior art circuit for implementing the switching of supply voltage levels is illustrated. FIG. 1 illustrates a prior art voltage level translator 100 for translating a voltage level from VCC to VSS (ground) to VCC to VBB. Upon assertion of the negative true logic signal IN on a line 105, a P-channel transistor 110, whose source is coupled to VCC on the line 103, is activated. Upon the assertion of IN (i.e., a transition from high to low of the signal IN on the line 105), a line 107 coupled to the drain of the transistor 110 is transitioned to a level of VCC. The complementary signal of IN, which is INB on a line 115, is sent to another P-channel transistor 120 whose source is coupled to VCC on a line 123. Upon the assertion of IN, the signal INB on the line 115 transitions to logic-high, therefore, the drain of transistor 120, which is coupled to a signal OUT on a line 135, is disconnected from VCC. The complementary signal to OUT on the line 135 is a signal OUTB on a line 125, which is the inverse of OUT.
The transition of the signal OUTB on the line 125, which is also coupled to a drain of an N-channel transistor 140, whose source is coupled to VBB via a line 145. Therefore, the N-channel transistor 140 will be turned off. At the same time, the complementary signal OUTB on the line 125 is also coupled to a gate 153 of a second N-channel transistor 150, whose source is coupled to VBB via a line 155. Therefore, during this time, when the complementary signal OUTB on the line 125 is high, the N-channel transistor 150 is turned on. When the N-channel transistor 150 is turned on, a connection to VBB to OUT on the line 135 is established. Therefore, an operating voltage level of VCC to VBB is established upon the assertion of IN on the line 105.
Currently, in order to implement the prior art voltage level translator 100, P-channel devices used in such circuits are usually substantially large. Therefore, there are transition delays due to these types of P-channel devices, which cause the transition from VCC to ground to VCC–VBB to be inefficient. Another problem is that when the voltage level translator 100 receives an input that goes to logic low (on the line 105), and the OUTB on the line 125 goes to logic high, this transition occurs in a substantially fast manner. However, the opposite state, where the output OUT on the line 135 transitions from logic low to a logic high state, there is a delay in the pull down because N-channel transistors are relatively weak compared to the typical P-channel transistors that are used. One of the reasons that the N-channels in the circuit are smaller is because the voltage level translator 100 may not properly switch if they are made of a similar size as the P-channel transistors. This could create a problem when the nodes of the output OUT, on the line 135 and OUTB on line 125 transition to a low state, and since transitioning to a low state is a very slow transition, the transition may occur fast enough to regain its voltage level back up to the level of VBB. Therefore, the transition going to VBB becomes too slow. This runs contrary to the motivation of switching from VCC to a VBB mode, therefore, a relatively fast switching is needed for proper voltage level transition for efficient operation of the circuitry supported by the voltage level translator 100.
These transition problems are exacerbated by the more recent drive to reduce the operating voltage level of VCC. Designers are generally pushing for lower and lower VCC levels, which causes even further delays in the transitions described above. This is true because if the P-channel transistors get weaker because VCC gets smaller, then there is very little gate-source voltage so the P-channels transistors have to make a bigger drive to make a proper transition. As the transition of the transistor moves from logic low to logic high, there is a drive that is pulling the transistor down, therefore, the transition is not properly made often, causing excessive current consumption. The industry generally lacks an efficient method and apparatus for translating efficiently from a voltage level of VCC to VSS to a voltage level of VCC to VBB.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.